1. Field of the Invention
The present invention relates generally to graphics instruction sets. More particularly, the present invention relates to an apparatus and method for implementing a pack instruction for a graphics instruction set.
2. The Prior Art
In graphics instruction sets, such as those provided in Sun Microsystems architecture, pixel formatting instructions include packing instructions which convert 16-bit or 32-bit data to a lower precision fixed or pixel format. Input values are clipped to the dynamic range of the output format. Packing applies a scale factor determined from a scale factor field in a Graphics Status Register (GSR) to allow flexible positioning of the binary point.
As it is desirable to so utilize packing instructions to enhance system performance, it is also desirable to optimize all elements carried out in such packing instructions to further enhance system performance. As is known, graphics instructions have a tendency to be resource intensive. Thus, better implementations of any or all elements within graphics units are desirable.
To overcome these and other shortcomings of the prior art, disclosed herein is an apparatus and method for providing a fast, small implementation of pack instructions. As part of the packing instruction in systems such as the Sun Microsystems MAJC, a 16-bit number consisting of two eight-bit bytes must be shifted by a specified amount to the xe2x80x9crightxe2x80x9d, resulting in an eight bit, one byte packed number. To achieve this result herein is disclosed a method and apparatus that performs this task by way of a predominantly parallel process which was heretofore unknown.
By implementing much of the process in a parallel manner, resource optimization is achieved. Such optimization results in, inter alia, faster processing of the pack in instruction, as well as enhanced parallel processing; thus, taking advantage of enhanced parallel processing devices to further optimize system performance.